Integrated circuits (ICs) may include defects and faults, which can alter their intended functionality and/or render them unusable. A defect can be an unintended physical change in the IC caused by an unintended aspect of a manufacturing process or a post-manufacturing overstress process, while a fault can be an unintended behavior of the IC, such as a circuit node stuck at a constant voltage. IC testing technology can perform tests on the ICs to detect a presence of a defect or a fault in the ICs.
Not all tests performed by the IC testing technology, however, are equivalent, as some tests may detect a presence of a defect or a fault when other tests would fail to detect the presence of the defect or fault. Fault simulation can measure or estimate a percentage of potential defects or potential faults in the IC that could be detected by a test applied to the IC and provide fault coverage for the test. Fault coverage can be a probability or a likelihood of the IC failing a test when the IC includes a defect or a fault. One technique of measuring fault coverage includes calculating a percentage of potential defects or potential faults that can be detected by the test, for example, dividing the number of defects or faults detected by the total number of potential defects simulated. The fault coverage calculation also may weight each potential defect or fault by its relative likelihood of occurring.
A fault simulator, for example, implemented by a computing system, can perform fault simulation on a circuit design for the IC, by selectively injecting faults into the circuit design for the IC, and simulating the IC based on the circuit design while applying a test and recording which of the injected faults were detected. The fault simulator can inject faults or defects into a design-intent netlist version of the circuit design, for example, specified at a transistor-level of abstraction, or into a physical-implementation netlist version, for example, generated by extracting design-intent elements and parasitic elements from a physical layout of the circuit design. Since the physical-implementation netlist includes parasitic elements, such as resistive, capacitive, and/or inductive elements introduced due to a geometric layout of the design, the fault simulation of the physical-implementation netlist can have a higher accuracy, but longer simulation time compared to the design-intent netlist.
Typically, the fault simulator can first simulate a netlist for the circuit design and a test without injecting any faults or defects. The fault simulator can then iteratively inject a defect or fault into different portions of the netlist for the circuit design and record whether the injected defect or fault was detected by the test. In some examples, the fault simulator, during simulation of the circuit design, can apply a test stimulus, such as sine waves or digital patterns, to the simulated circuit design, measure signals of the circuit design in response to the test stimulus, and determine parameters of the signals, for example, output signal amplitude, delay, or the like. The fault simulator also can calculate parameter values from the measurements, such as a gain value, which corresponds to the output signal amplitude divided by an input signal amplitude, or the like, and attempt to detect the defect or the fault in the simulated IC by comparing each parameter or parameter value to lower and/or upper test limits.